1. Field of the Invention
Embodiments of the invention relate to a method for manufacturing integrated circuit devices. More particularly, embodiments of the invention relate to a method for forming metal interconnects.
2. Description of the Related Art
Sub-quarter micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (VLSI). The multilevel interconnects that lie at the heart of this technology possess high aspect ratio features, including contacts, vias, lines, or other apertures. Reliable formation of these features is very important to the success of VLSI and to the continued effort to increase quality and circuit density on individual substrates. Therefore, there is a great amount of ongoing effort being directed to the formation of void-free features having high aspect ratios (height:width) of 4:1 or greater.
The presence of native oxides and other contaminants within a feature causes problems during fabrication. For example, the presence of native oxides and other contaminants within a feature creates voids by promoting uneven distribution of a depositing layer. The presence of native oxides and other contaminants can also reduce the electromigration resistance of vias and small features. Further, the presence of native oxides and other contaminants can diffuse into the dielectric layer, the sublayer, or the depositing layer and alter the performance of the device. Typically, native oxides are formed when a substrate surface having a nonconductive layer (silicon, silicon oxide) or a conductive layer (aluminum, tungsten, titanium, tantalum, tungsten, copper) disposed thereon, is exposed to oxygen in the atmosphere or is damaged in a plasma etch step. The xe2x80x9cother contaminantsxe2x80x9d may be generated from sputtered material from an oxide over-etch, residual photoresist from a stripping process, leftover polymer from a previous oxide etch step, or redeposited material from a preclean sputter etch process, for example.
A typical process for forming an interconnect on a substrate includes depositing one or more layers, etching at least one of the layer(s) to form one or more features, depositing a barrier layer in the feature(s) and depositing one or more layers to fill the feature. Copper and its alloys have become the metals of choice for filling sub-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 xcexcxcexa9-cm compared to 3.1 xcexcxcexa9-cm for aluminum), a higher current carrying capacity, and a significantly higher electromigration resistance. Copper also has good thermal conductivity and is available in a highly pure state.
However, copper readily forms oxides when exposed to atmospheric conditions. Copper oxides increase the resistance of metal layers, become a source of particle problems, and reduce the reliability of the overall circuit. Copper oxides may also interfere with subsequent deposition processes.
One solution to prevent the formation of copper oxides is to deposit a passivation layer or encapsulation layer over the copper layer. A passivation layer isolates copper surfaces from ambient oxygen. Cobalt and cobalt alloys have been observed as suitable materials for passivating copper and may be deposited on copper by electroless deposition techniques. However, copper does not satisfactorily catalyze or initiate deposition of cobalt and cobalt alloys from electroless solutions.
To counteract this problem, a common approach has been to activate the copper surface by first depositing a catalytic material on the copper surface. The deposition of the catalytic material typically requires multiple, time consuming steps and, most times, the use of catalytic colloid compounds. Catalytic colloid compounds can adhere to dielectric materials and produce undesired, excessive, and non-selective deposition of passivating material on the substrate surface. Non-selective deposition of passivating material, such as deposition on dielectric materials, may lead to surface contamination, unwanted diffusion of conductive materials into dielectric materials, and even device failure from short circuits and other device irregularities.
There is a need, therefore, for a method for selectively depositing a passivation layer on a conductive substrate using one or more electroplating techniques.
Embodiments of the invention provide a method for depositing a passivation layer on a substrate surface using one or more electroplating techniques. In one aspect, the method includes selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution.
In another aspect, the method includes polishing a substrate surface to expose a conductive material disposed in a dielectric material, exposing the substrate surface to a first acidic solution, selectively depositing an initiation layer on the conductive material by exposing the substrate surface to a first electroless solution, electrolessly depositing a passivating material comprising cobalt or a cobalt alloy on the initiation layer, and cleaning the substrate surface with a second acidic solution.
In yet another aspect, the method includes cleaning a substrate surface with a first acidic solution, selectively depositing a noble metal selected from the group of palladium, platinum, alloys thereof, and combinations thereof on the substrate surface by exposing the substrate surface to an acidic electroless solution containing a noble metal salt and an inorganic acid, electrolessly depositing cobalt or a cobalt alloy on the noble metal, cleaning the substrate surface with a second acidic solution, and applying ultrasonic or megasonic energy to the substrate surface while cleaning the substrate surface with the second acidic solution.